| 摘要 |
<p>Among the embodiments of the present invention, is memory control circuitry (40) that includes a detection circuit (44) and a monostable multivibrator (104). This detection circuit (40) is responsive to a transition of a number of address inputs to generate a trigger signal. The monostable multivibrator (104) is responsive to the trigger signal to change a memory control output signal from a first state to a second state. The monostable multivibrator (40) is further responsive to a memory interlock input signal to change the memory control output signal from the second state to the first state. The memory control circuitry (40) can be coupled to drive a clock input of a synchronous memory (30) to provide for asynchronous operation thereof.</p> |
