| 摘要 |
A digital phase detector that conducts pump up and pump down control signals to a charge pump, wherein each of the control signals has pulses that have a substantially 50/50 duty cycle characteristic when the two input signals, i.e., the input data signal and the feedback clock signal, are substantially in phase. This substantially 50/50 duty cycle output reduces, if not eliminates, inherent problems related to the turn-on delays of the charge pump while maintaining a locked condition. The phase detector may further include an intelligence to detect and handle other situations, such as missing data pulses.
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