发明名称 Data receiver capable of invalidating erroneous pulses
摘要 In a data receiver, pulse edges are sequentially detected from the pulse string. If a pulse which has a width equal to two cycles of the reference clock signals is detected, bit data "1' is restored. If two consecutive pulses each of which has a width equal to one cycle are detected, bit data "0' is restored. If a pulse width between two consecutive pulse edges is not equal to one cycle or two cycles, it is presumed that a pulse edge of an erroneous pulse is detected. If the pulse width between the pulse edge, which is presumed to correspond to the erroneous pulse, and the next pulse edge is equal to or shorter than a predetermined threshold Th, the pulse edge and the next pulse edge is invalidated.
申请公布号 US2002084841(A1) 申请公布日期 2002.07.04
申请号 US20010001810 申请日期 2001.12.05
申请人 TAGUCHI AKIHIRO;TSUJI HIROYUKI 发明人 TAGUCHI AKIHIRO;TSUJI HIROYUKI
分类号 H03K5/1532;B60C23/04;H03K5/1252;H04L1/24;H04L25/03;H04L25/38;H04L25/48;H04L25/49;(IPC1-7):H04L27/06 主分类号 H03K5/1532
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