| 摘要 |
<p>A semiconductor integrated circuit comprising a timing control circuit for producing a clock signal having a proper phase proper for sampling an input signal even if the input signal have a large waveform distortion or jitter. This semiconductor integrated circuit comprises at least one integrating means for integrating the relative level of the input signal for a period between two consecutive pulses of the clock signals at least one detecting means for detecting a transition of the input signal for the period of the two consecutive pulses of the clock signal, to output a detection signal corresponding to the transition direction, at least one switch means for inverting the output signal of said at least one integrating means in accordance with the detection signal outputted from the at least one detecting means, and phase control signal generating means for generating a phase control signal used for controlling the phase of the clock signal, according to the output signal of the at least one switch means.</p> |
