发明名称 |
Burst access memory with zero wait states |
摘要 |
A memory device has a segmented memory cell array that take a row address and a column address and allows for data words in a column page to be read internally in parallel for faster access. The memory device employs a segmented memory array that routes column address and column address+1 to the segments. This allows for a random starting data word in the column page, while the data words in the next column page (column address+1) are loaded into the memory array segments before the starting data word. When the data page mode or linear burst access crosses a column address boundary the next data words in column address+1 are available and no wait states need to be asserted to allow for new column address values to propagate.
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申请公布号 |
US2002085417(A1) |
申请公布日期 |
2002.07.04 |
申请号 |
US20000751688 |
申请日期 |
2000.12.29 |
申请人 |
PEKNY THEODORE T.;GUALANDRI STEPHEN J. |
发明人 |
PEKNY THEODORE T.;GUALANDRI STEPHEN J. |
分类号 |
G11C7/10;G11C8/12;G11C16/08;(IPC1-7):G11C16/04 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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