发明名称 |
System and method for employing a process identifier to minimize aliasing in a linear-addressed cache |
摘要 |
A system and method for reducing linear address aliasing is described. In one embodiment, a portion of a linear address is combined with a process identifier, e.g., a page directory base pointer to form an adjusted-linear address. The page directory base pointer is unique to a process and combining it with a portion of the linear address produces an adjusted-linear address that provides a high probability of no aliasing. A portion of the adjusted-linear address is used to search an adjusted-linear-addressed cache memory for a data block specified by the linear address. If the data block does not reside in the adjusted-linear-addressed cache memory, then a replacement policy selects one of the cache lines in the adjusted-linear-addressed cache memory and replaces the data block of the selected cache line with a data block located at a physical address produced from translating the linear address. The tag for the cache line selected is a portion of the adjusted linear address and the physical address produced from translating the linear address.
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申请公布号 |
US2002087824(A1) |
申请公布日期 |
2002.07.04 |
申请号 |
US20000751258 |
申请日期 |
2000.12.29 |
申请人 |
HUM HERBERT H.J.;JOURDAN STEPHAN J.;HAMMARLUND PER H. |
发明人 |
HUM HERBERT H.J.;JOURDAN STEPHAN J.;HAMMARLUND PER H. |
分类号 |
G06F12/10;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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