| 摘要 |
A clock interruption detection circuit comprises a frequency divider circuit for outputting a plurality of frequency divided clocks by dividing an input clock with different division values, an AND circuit for ANDing the Input clock and the plurality of frequency divided clocks, an Inverter for inverting one of the frequency divided clocks with the largest division value, another AND circuit for ANDing the input clock, the rest of the frequency divided clocks and the output of the inverter, a first and a second switch with a control terminal supplied with the output of each of the AND circuits for controlling the on/off of a discharge path of a first and a second capacitor, a first and a second waveform-shaping buffer circuit supplied with a terminal voltage of the first and the second capacitor, and a selection circuit for selecting one of the outputs of the first and second waveform-shaping buffer circuits In accordance with a selection control signal obtained by delaying the output of the inverter by a predetermined length of time in a delay circuit. The clock interruption detection circuit enables a clock Interruption to be detected by a single system of input clock, makes integration easier and allows the clock interruption time to be detected accurately.
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