Clock regeneration in an Orthogonal Frequency Division Multiplex (OFDM) receiver

摘要

Received OFDM signals are subjected to discrete Fast Fourier transformation (FFT). Frequency component data of a pilot sub-carrier and those of a previous pilot sub-carrier temporarily stored in RAMs 6, 7 are subjected to complex multiplication 11 and fed to ROM 12. The ROM reads out phase fluctuations between adjoining pilot signals (see figure 4) in a common symbol to an adder 15 which accumulates the phase fluctuation data for one symbol period. An offset adder 16 adds a predetermined offset to the accumulated phase fluctuation to align the FFT time window. The result is used to control the frequency of the sampling clock signal (166, figure 2). The circuit is able to generate a clock signal having neither a frequency error nor a phase error.