| 摘要 |
A technique is provided for laying out vias between metal layers in an integrated circuit structure utilizing conventional Metal n and Metal N+1 databases. A first database (Metal n) is created that defines a lower conductive layer. A second database (Metal N+1) is created that defines an upper conductive layer. Selected intersections of the first database and the second database are then determined, thereby creating a third database (via n) that defines a pattern of vias between the lower conductive layer and the upper conductive layer. This allows interconnect vias to be optimized in size and shape, thus providing lowest possible interlayer resistance, which in turn provides the best possible circuit performance and reliability.
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