| 摘要 |
A latch and a D-type flip-flop capable of realizing high speed operation and capable of achieving a reduction of power consumption, wherein in a master side latch, a first NMOS transistor always in the ON state is provided as a first parallel resistor means connected in parallel with a second NMOS transistor (serving as the first input discriminating means) receiving a data input signal D, and a third NMOS transistor always in the ON state is provided as a second parallel resistor means connected in parallel with a fourth NMOS transistor NT114 (serving as the first input discriminating means) receiving an inverted data input signal DX. By this, without enlarging the transistor sizes of the second and fourth NMOS transistors, an equivalent combined resistance of discharge paths can be reduced by these parallel resistor means, a high speed operation can be realized, and a lowering of a power consumption can be realized.
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