Clock generation circuit, serial/parallel conversion device and parallel/serial conversion device together with semiconductor device

摘要

A clock generation circuit that generates multi-phase output clock signals which immediately follow any change in the period of an input clock signal. This clock generation circuit comprises a voltage-controlled oscillator (14) that generates an output signal having a frequency that varies in response to a control voltage; a phase comparator (11) that compares the phase of the input clock signal and the phase of the output signal of the voltage-controlled oscillator, to detect the phase difference therebetween; control voltage generation circuits (12, 13) that generate a control voltage corresponding to that phase difference; and a variable delay circuit (15) that generates multi-phase output clock signals by delaying the input clock signal in accordance with the control voltage.