发明名称 Digital signal multiplier
摘要 An electronic circuit that multiplies an input signal using primarily digital components so that the resulting circuit can be fabricated consistently by different foundries. The circuit determines a period for the input signal and converts the period to a digital number (e.g., a binary number). An adder is used to determine an average period over a predetermined number of cycles. By determining the average period, voltage fluctuations are cancelled. A multiplier allows for a variable multiplication of the averaged period. A clock generating circuit uses the results obtained by the multiplier to generate a multiplied output signal. Additionally, the input signal is routinely multiplexed with the generated output signal to ensure phase matching.
申请公布号 US6415008(B1) 申请公布日期 2002.07.02
申请号 US19980212052 申请日期 1998.12.15
申请人 BéCHADE ROLAND ALBERT;CHEPONIS RONALD JOSEPH 发明人 BéCHADE ROLAND ALBERT;CHEPONIS RONALD JOSEPH
分类号 H04L25/03;(IPC1-7):H04L27/06 主分类号 H04L25/03
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