| 摘要 |
An interrupt controller for a microprocessor having a plurality of event memories which are combined to form at least one group and each having an input for a setting signal and an output for an event memory signal which portrays the state of the event memory. The setting signal for an event memory becomes active when activation of an event signal associated with this event memory is detected. The event memory signals are connected to an interrupt signal for the microprocessor. The microprocessor has read and write access to the event memory signals via a data bus. The event memories each have an input for a resetting signal. The resetting signal in a group becomes active when the microprocessor effects write access to the group containing this event memory using a first write signal and, at the same time, that individual signal from the microprocessor which is associated with this event memory is active on the data bus. A means for ensuring that the resetting signal for an event memory becomes not active if the state of an event memory 40 is altered by new events during reading or between reading and resetting the event memory 40. |
