发明名称 METHOD OF MANUFACTURING MULTILAYER WIRING BOARD
摘要 <p>PROBLEM TO BE SOLVED: To provide a multilayer wiring board manufacturing method capable of improving a multilayer wiring board in dimensional accuracy and reducing production processes in number. SOLUTION: The formation of a viahole 17a and the flattening operation of the projection of an insulating film photosensitive varnish 7a are performed at the same time by carrying out an light exposure process, and a developing process by the use of a photomask which is so designed as to be composed of a light transmitting film 9, a 67% light transmitting film 11, a 20% light transmitting film 10, and a light shielding film 8 which are stacked up in this sequence for each of a flat 12, a slope 13, a protuberant flat 14, and a viahole forming predetermined point 15. By this setup, production processes can be reduced in number, and an exposure process can be reduced in frequency, so that a multilayer wiring board can be improved in dimensional accuracy.</p>
申请公布号 JP2002185138(A) 申请公布日期 2002.06.28
申请号 JP20000380455 申请日期 2000.12.14
申请人 NEC CORP 发明人 KASUYA KAZUHIRO
分类号 G03F1/54;G03F7/20;H01L23/12;H05K3/00;H05K3/40;H05K3/46;(IPC1-7):H05K3/46;G03F1/08 主分类号 G03F1/54
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