| 摘要 |
PROBLEM TO BE SOLVED: To provide pipelines capable of asserting a stall signal by either of the pipelines and any cycle which is not an object of stall by itself. SOLUTION: A processor consisting of many pipelines having many pipeline stages (142, 146) each of which is to execute instructions with continuous clock cycles is disclosed. The processor allows temporary loss of harmonization of an instruction of one pipeline with an instruction of the other instruction. The processor allows time for a global signal to be supplied such as a global stall signal.
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