| 摘要 |
When a plurality of output buffer circuits are provided, chip layout size, power consumption, and number of pins of an LSI circuit are reduced. A voltage generation circuit generates reference voltages corresponding respectively to the output buffer circuits. A comparison circuit compares the reference voltages with an output voltage of a dummy buffer circuit. A counter counts a clock signal until a comparison result of the comparison circuit matches. The dummy buffer circuit adjusts output impedance corresponding respectively to the output buffer circuits based on a count value of the counter. Adjustment value holders hold respective count values when a comparison result of the comparison circuit, obtained based on respective corresponding reference voltages, matches. The output buffer circuits respectively adjust output impedances based on respectively held count values.
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