| 摘要 |
The frequency synthesizer is based on a phase-locked loop (PLL) comprising an integer-ratio frequency divider (14) connected to a phase-frequency comparator (16), a sigma-delta modulator (30) connected to the frequency divider in order to obtain a mean division ratio with a fractional component, a constant fractional-ratio frequency divider (100), and computing units (40,120) connected so to activate the fractional-ratio frequency divider whenn the fractional component (k) of the mean division ratio is contained in at least one range of determined values, and to modify a tuning instruction (K') in a corresponding manner. The constant fractional division ratio is equal to 1+(epsilon), and the range of determined values of the fractional component (k) comprises values in the intervals (0, (epsilon)/2) and (1-(epsilon)/2,1), where (epsilon) is strictly between 0 and 1, in particular equal to 0.5. The computing unit (40) is for computing the division ratio and for controllling the fractional-ratio frequency divider (100) The sigma-delta modulator (30) is in two stages. A latch (52) is for setting to 1 the value of the least significant bit of the tuning instruction. The method for frequency synthesis is implemented by the frequency synthesizer. A frequency converter comprises a mixer with the first input connected to a source of signal for conversion, and the second input connected to a source of reference-frequency signal, which comprises the frequency synthesizer.
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