发明名称 CIRCUIT LOGIQUE A POLARITE VARIABLE
摘要 The invention concerns a method for jamming the operating conditions of a logic circuit (30) designed to execute a specific logic function. The invention is characterised in that it consists in: providing in the logic circuit logic gates (10) and/or transistors adapted to execute the logic function at least in two different ways, the way in which the logic function is executed being determined by the value of a function selecting signal (R) applied to the logic circuit; then in applying to the logic circuit a random function selecting signal (R), and in refreshing the function selecting signal at specific times, so as to jam the operating conditions of the logic circuit. Thus, for identical data applied to the logic circuit input and different values of function selecting signal, the polarities of certain internal nodes of the logic circuit and/or the logic circuit power consumption are not identical.
申请公布号 FR2818847(A1) 申请公布日期 2002.06.28
申请号 FR20000017002 申请日期 2000.12.26
申请人 STMICROELECTRONICS SA 发明人 WUIDART SYLVIE
分类号 G06F7/00;G06F21/72;G06F21/75;G07F7/10;(IPC1-7):H04L9/32 主分类号 G06F7/00
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