发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a PLL circuit which reduces hops of phase in the output of a voltage control oscillator which are generated by a voltage noise due to the expansion or the constriction of circuit devices when the ambient temperature suddenly changes. SOLUTION: A phase comparator 2 receives an input signal as the reference frequency and an output signal outputted from a voltage control oscillator 11 and compares phases of the two signals. A loop filter 3 receives the output of the phase comparator 2 and outputs a phase control signal. A lag lead filter 12 connects a capacitor 53 in parallel with a resistor 51 which constitutes a low-pass filter with a capacitor 52 and its cutoff frequency is set to at least 10 times as high as the loop band frequency. The voltage control oscillator 11 is controlled by the phase control signal and outputs the output signal.
申请公布号 JP2002185315(A) 申请公布日期 2002.06.28
申请号 JP20000385516 申请日期 2000.12.19
申请人 NEC CORP 发明人 WATABE JUNJI
分类号 H03L7/093 主分类号 H03L7/093
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