发明名称 |
DMA COMMUNICATION CONTROLLING METHOD, TRANSFERRED DATA PROCESSING METHOD AND ENGINE CONTROLLER |
摘要 |
PROBLEM TO BE SOLVED: To provide a DMA communication controlling method which is capable of preventing the delay of processing to be performed without synchronizing with time such as A/D conversion processing synchronizing with engine rotation and capable of reducing the processing load of a CPU. SOLUTION: This method includes a step for dividing time synchronizing data into two groups and requesting a DMAC 16 to process the time synchronizing data belonging to a former half group in synchronization with time, a step for requesting the DMAC 16 to process the time synchronizing data belonging to a latter half group in synchronization not with time but with a prescribed timing and a step for requesting the DMAC 16 to process the non-time synchronizing data in synchronization with the prescribed timing. The processing request for the non-time synchronizing data is preferential to that for the time synchronizing data.
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申请公布号 |
JP2002183077(A) |
申请公布日期 |
2002.06.28 |
申请号 |
JP20000376791 |
申请日期 |
2000.12.12 |
申请人 |
FUJITSU TEN LTD |
发明人 |
SHIROTA YASUHIRO;IMADA SHOGO |
分类号 |
G06F3/05;G06F13/28;H03M1/12;(IPC1-7):G06F13/28 |
主分类号 |
G06F3/05 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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