发明名称 |
DUTY CYCLE CORRECTING CIRCUIT AND METHOD |
摘要 |
A duty cycle correcting circuit includes a duty detector that detects a duty ratio of an output clock signal to output a duty detection signal, a variable delay unit that outputs a delay clock signal obtained by variably delaying a input signal according to the duty detection signal, and a pulse width modulating unit that generates a first clock signal that is at a high level when both the input clock signal and the delay clock signal are at a high level and generates a second clock signal that is at a high level when any of the input clock signal and the delay clock signal is at a high level, wherein the pulse width modulating unit selectively outputs the first clock signal or the second clock signal as the output clock signal.
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申请公布号 |
US2009058483(A1) |
申请公布日期 |
2009.03.05 |
申请号 |
US20080200747 |
申请日期 |
2008.08.28 |
申请人 |
HYNIX SEMICONDUCTOR, INC. |
发明人 |
SHIN DONG-SUK;LEE HYUN-WOO;YUN WON-JOO |
分类号 |
H03K3/017 |
主分类号 |
H03K3/017 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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