Information processing system with prefetch instructions having indicator bits specifying cache levels for prefetching

摘要

For improving the performance of an information processing unit having caches, indication bits for indicating a hierarchical level of a cache to which an operand data is to be transferred or for indicating a quantity of an operand data to be transferred or for indicating both are provided in a software prefetch instruction, and at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction.