| 摘要 |
A DRAM device (200) is disclosed having a plurality of memory cells (208) formed on a substrate (202). Each memory cell (208) includes a transistor (210) having a gate (212), and a storage capacitor (214) having a bottom plate (226) covered with a capacitor dielectric (234). A relatively thin top plate (236) is formed over a number of memory cells (208) in a array portion (204) of the DRAM device (200). The top plate (236) extends to a peripheral array portion (206) where contact is made thereto by metallization (248), by way of a plate contact hole (244). An etch stop (240), formed from the same layer as the gate (212) in the preferred embodiment, is disposed in the peripheral array portion (206) below the plate contact hole (244). The etch stop (240) provides greater flexibility in the plate contact hole etching step, by preventing the plate contact hole (244) from extending through the top plate (236) and to the substrate (202).
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