Demodulator and method for second harmonic cancellation

摘要

A demodulator circuit (10) having harmonic cancelling receives an input signal (IF) and generates an oscillator signal (OSC) in an oscillator circuit (14). The oscillator signal (OSC) is locked to the same frequency and phase as the input signal (IF). A phase shift circuit (18) generates a shifted signal (OSC SHIFTED) that is in quadrature with the oscillator signal (OSC). A multiplier (22) receives the oscillator signal (OSC) and the shifted signal (OSC SHIFTED) and generates an output signal (21F) having twice the frequency of the oscillator signal (OSC). A multiplier circuit (24) also receives the input signal (IF) and along with the oscillator signal (OSC) generates an output signal (PD). The signals generated by the multiplier (22) and the multiplier circuit (24) are summed in a summing circuit (30) that supplies an output signal (OUT).