发明名称 Integrated circuit having synchronized pipelining and method therefor
摘要 Briefly, in accordance with one embodiment of the invention, a integrated circuit may generate and store a synchronization signal. This synchronization signal may be used as an enable signal to generate other synchronization signals in subsequent cycles of a clock signal.
申请公布号 US2002080655(A1) 申请公布日期 2002.06.27
申请号 US20000750389 申请日期 2000.12.27
申请人 CLARK LAWRENCE T.;MILLER JAY B. 发明人 CLARK LAWRENCE T.;MILLER JAY B.
分类号 G06F12/08;(IPC1-7):G11C7/00 主分类号 G06F12/08
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