发明名称 Method for tuning a PLL circuit
摘要 In the previously known methods for tuning the PLL circuit, the loop filter has to be discharged again if the PLL circuit does not lock in. During this time, also known as dead time, the PLL circuit cannot detect any signals. With the new method, the PLL circuit can also detect signals during the discharge period of the loop filter. This avoids dead times and the signal detection by the PLL circuit is substantially accelerated. The data throughput is increased, especially when used in high-frequency applications such as, for example, in the field of mobile telephones.
申请公布号 US2002079974(A1) 申请公布日期 2002.06.27
申请号 US20010996521 申请日期 2001.11.28
申请人 ATMEL GERMANY GMBH 发明人 BERGMANN GUENTHER;GRUSON FRANK
分类号 H03L7/12;(IPC1-7):H03L7/00 主分类号 H03L7/12
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