Fast fourier transform processor using high speed area-efficient algorithm

摘要

The present invention discloses a fast Fourier transform (FFT) processor using a high speed area-efficient algorithm. The FFT processor is embodied by using the algorithm including a radix-4 butterfly module for receiving four input signals, and performing a butterfly operation thereon, and a radix-2 butterfly module connected to the radix-4 butterfly module, for performing the butterfly operation on the output signals from the radix-4 butterfly module. As a result, a number of nontrivial complex multipliers is reduced, to perform the FFT in a high speed in a small area.