发明名称 |
GLOBAL SIGNAL DISTRIBUTION ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY |
摘要 |
A global signal distribution architecture for an FPGA architecture that has a plurality of multiplexers (80) with inputs and an output. The outputs of the plurality of multiplexers (80) are coupled to global I/O lines (16) that are coupled to a global signal distribution bus (18) spanning a highest level in the FPGA architecture. A plurality of switch matrices (106) are coupled to global signal distribution bus (18) and to a plurality of utility conductors (108) that are coupled to at least one multiplexer associated with a lowest level in the FPGA architecture.
|
申请公布号 |
WO0049718(A9) |
申请公布日期 |
2002.06.27 |
申请号 |
WO2000US04477 |
申请日期 |
2000.02.22 |
申请人 |
|
发明人 |
KUNDU, ARUNANGSHU;BAKKER, GREGORY, W.;WONG, WAYNE |
分类号 |
H03K19/177;(IPC1-7):H03K19/177;H01L25/00 |
主分类号 |
H03K19/177 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|