CONTROLLED ANNEAL CONDUCTORS FOR INTEGRATED CIRCUIT INTERCONNECTS

摘要

A method is provided for manufacturing an integrated circuit on a semiconductor wafer (200) having a semiconductor substrate with a semiconductor device thereon. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier (226, 232) layer is deposited to line the opening. A seed layer (228, 234) is deposited on the barrier layer and securely bonds to the barrier layer. A conductor (230, 236) layer is deposited to fill the channel opening over the barrier layer. A planarization technique is used to planarize the barrier, seed layer, and conductor layers to be coplanar with the dielectric layer to form a conductor channel. The semiconductor wafer is then subjected to a two step timed anneal.