| 摘要 |
PROBLEM TO BE SOLVED: To provide a test architecture performing a boundary test when an integrated circuit is set in an operation mode. SOLUTION: The test architecture is equipped with the application logical circuit of an integrated circuit having input and output terminals, a serial scanning route formed from the test cell register of the integrated circuit and the buffer memory connected to the serial scanning route in order to receive the data bit from the serial scanning route to output the same. The test cell register has functional data input, functional data output, serial test data input and serial test data output and is connected to the serial test data output of one test cell register connected to the serial test data input of a separate test cell register. The buffer memory has a sufficient memory space in order to store at least one data bit with respect to each test cell register of one input group. |
