| 摘要 |
<p>PROBLEM TO BE SOLVED: To obtain a clock switching circuit capable of reducing the circuit scale, enhancing the signal transmission efficiency and improving the layout area efficiency. SOLUTION: This clock switching circuit consists of a NAND circuit 12 and a NOR circuit 13 to which an output of an inverter circuit 11 is inputted, a DFF 14 to which an output of the NAND circuit 12 is inputted, a DFF 15 to which an output of the NOR circuit 13 is inputted, an inverter circuit 16 to which an output of the DFF 14 is inputted, a clock signal selecting part 17a to which outputs of the DFF 15 and the inverter circuit 16 are inputted and an inverter circuit 20 to which an output of the selecting part 17a is inputted.</p> |
