Optimized parallel in parallel out GF(2M) squarer for FEC decoder

摘要

The present invention achieves technical advantages as a squarer circuit. The squarer circuit is utilized to square GF (2<13>) vectors in order to implement the sigma calculations and a Chien search. Gates are optimized to provide an advantageous latency squaring circuit. Customized cells are utilized such that the squarer takes two inputs to be multiplied, and outputs the results in only one clock cycle. This solution is custom for GF (2<13>) vectors. For other powers, the same methodology can be implemented although the resulting gates will be different. The squarer circuit is customized to operate with OC-48 and OC-192 data, and is operable to meet both the SONET Standard T1X1.5/99-218R3 and the SDH Standard. <IMAGE>