| 摘要 |
A non-volatile latch comprises first and second read/write bias nodes and first and second a complementary output nodes. First and second first conductivity type MOS transistors have sources coupled to a first voltage potential. A drain of the first MOS transistor is coupled to the first complementary output node and a drain of the second MOS transistor is coupled to the second complementary output node. Each of the first and second MOS transistors have a gate cross coupled to the drain of the other one of the first and second MOS transistor. A source of a third MOS transistor is coupled to the first read/write bias node and a source of a fourth MOS transistor is coupled to the second read/write bias node. A drain of the third MOS transistor is coupled to the first complementary output node and a drain of the fourth MOS transistor is coupled to the second complementary output node. Each of the third and fourth MOS transistors have a gate cross coupled to the source of the other one of the third and fourth MOS transistors.
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