发明名称 PLL control method in data receiving apparatus
摘要 Disclosed is a PLL control method of controlling a phase of a PLL for taking synchronism of a receiving signal in a data receiving apparatus. The phase of the PLL is synchronized with a phase when training irrespective of a line characteristic. The PLL control method comprises a step of training a timing phase of PLL in accordance with a training signal, a step of obtaining, immediately after training, a right-side reference value from a sum of tap coefficients of taps on the right side of a center tap of the auto equalization unit, and obtaining a left-side reference value from a sum of tap coefficients of taps on the left side of the center tap of said auto equalization unit, a step of calculating a sum of the tap coefficients of the taps on the right side of the center tap of the auto equalization unit, thereafter obtaining a first difference between the above sum and a right-side reference value, calculating a sum of the tap coefficients of the taps on the left side of the center tap of the auto equalization unit, and thereafter obtaining a second difference between the above sum and a left-side reference value, and a step of obtaining a PLL control signal by obtaining a difference between the first and second differences.
申请公布号 US6411650(B1) 申请公布日期 2002.06.25
申请号 US19980192429 申请日期 1998.11.16
申请人 FUJITSU LIMITED 发明人 OKITA RYOJI
分类号 H03L7/08;H03L7/06;H04B3/10;H04L7/02;H04L7/033;H04L27/22;H04L27/38;(IPC1-7):H03H7/30;H03H7/40;H03H5/159 主分类号 H03L7/08
代理机构 代理人
主权项
地址