发明名称 |
Lock detector for a dual phase locked loop system |
摘要 |
A dual phase locked loop (PLL) lock detector is disclosed using a single lock detector to determine whether a dual PLL system is in a lock condition. In one embodiment, a VCO clock output from a master PLL is frequency divided to form a reference clock for a slave PLL. The lock detector monitors the slave PLL only when it determines that the master PLL is locked.
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申请公布号 |
US6411143(B1) |
申请公布日期 |
2002.06.25 |
申请号 |
US20010957201 |
申请日期 |
2001.09.19 |
申请人 |
MICREL, INCORPORATED |
发明人 |
FERNANDEZ-TEXON FRANCISCO |
分类号 |
H03L7/095;H03L7/23;(IPC1-7):H03L7/06 |
主分类号 |
H03L7/095 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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