发明名称 Fully integrated ethernet transmitter architecture with interpolating filtering
摘要 A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is interpolated by N and processed by a digital filter to obtain the pulse shape required by the particular communication application. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. When implemented in such manner, the logical implementation and memory replaces digital filtering circuits, DAC decoding logic circuit and re-synchronization logic circuits that are conventionally implemented in hardware. Thus, the hardware functionality of these circuits is rendered into arithmetic form and implemented in a memory device.
申请公布号 US6411647(B1) 申请公布日期 2002.06.25
申请号 US19990429887 申请日期 1999.10.29
申请人 发明人
分类号 H04B1/38;H04B3/00;H04B3/23;H04B15/00;H04J11/00;H04L5/16;H04L12/10;H04L25/00;H04L25/02;H04L25/03;H04L25/08;H04L25/14;H04L25/49;H04L27/00;H04L27/04;(IPC1-7):H04L27/00 主分类号 H04B1/38
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