| 摘要 |
A dual-modulus prescaler for a RF frequency synthesizer, which may operate in a high speed and reduce energy consumption with use of a selective latching technique includes a first frequency-dividing circuit for being synchronized to the clock signal to generate a latch control signal, latching the clock signal at a leading edge of the generated latch control signal, changing the frequency-dividing mode from a first frequency-dividing mode to a second frequency-dividing mode when latching the clock signal, and frequency-dividing and outputting the clock signal; a second frequency-dividing circuit for frequency-dividing the frequency divided signal from the first frequency-dividing circuit at a predetermined frequency-dividing ratio and outputting a plurality of frequency divided signals; and a logic operation circuit for logically operating a plurality of the frequency divided signals and the mode control signal to control the frequency-dividing mode of the first frequency-dividing circuit.
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