Multiple threshold voltage semiconductor device

摘要

In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, a second field effect transistor formed in the substrate structure, and a third field effect transistor formed in the substrate structure. The first field effect transistor can include a first gate stack configuration, and a first threshold voltage. The second field effect transistor can include a second gate stack configuration, and a second threshold voltage. The third field effect transistor can include a third gate stack configuration, and a third threshold voltage.

主权项

1. A semiconductor device comprising:
a substrate structure; a first field effect transistor formed in the substrate structure, a second field effect transistor formed in the substrate structure, and a third field effect transistor formed in the substrate structure, wherein each of the first field effect transistor, the second field effect transistor and the third field effect transistor have a first common channel polarity; a fourth field effect transistor formed in the substrate structure, a fifth field effect transistor formed in the substrate structure, and a sixth field effect transistor formed in the substrate structure, wherein each of the fourth field effect transistor, the fifth field effect transistor and the sixth field effect transistor have a second common channel polarity; wherein the first field effect transistor includes a first gate stack configuration and wherein the first field effect transistor is configured to have a first threshold voltage; wherein the second field effect transistor includes a second gate stack configuration and wherein the second field effect transistor is configured to have a second threshold voltage higher than the first threshold voltage; wherein the third field effect transistor includes a third gate stack configuration and wherein the third field effect transistor is configured to have a third threshold voltage higher than the second threshold voltage; wherein the fourth field effect transistor includes a fourth gate stack configuration and wherein the fourth field effect transistor is configured to have a fourth threshold voltage; wherein the fifth field effect transistor includes a fifth gate stack configuration and wherein the fifth field effect transistor is configured to have a fifth threshold voltage higher than the fourth threshold voltage, the fifth gate stack comprising a dielectric layer, a first conductive layer overlying the dielectric layer, a second conductive layer overlying the first conductive layer, a third conductive layer overlying the second conductive layer, a fourth conductive layer overlying the third conductive layer, and a filler conductive layer overlying the fourth conductive layer; wherein the sixth field effect transistor includes a sixth gate stack configuration and wherein the sixth-field effect transistor is configured to have a sixth threshold voltage higher than the fifth threshold voltage, the sixth gate stack comprising the fifth gate stack absent the first conductive layer; wherein the first gate stack comprises the fifth gate stack absent one of the third and the first conductive layers and the third and the second conductive layers; wherein the second gate stack comprises the fifth gate stack absent the first and the third conductive layers; wherein the third gate stack comprises the fifth gate stack absent the third conductive layer; and wherein the fourth gate stack comprises the fifth gate stack absent the second and the third conductive layers.