| 摘要 |
PURPOSE: A method for fabricating an interlayer dielectric of a semiconductor device is provided to decrease parasitic capacitance, by generating a void in a plasma enhanced tetra ethyl ortho silicate(PETEOS) insulation layer deposited between metal interconnections. CONSTITUTION: A semiconductor substrate(1) is prepared in which a metal interconnection of a predetermined pattern is formed on the interlayer dielectric(2). The PETEOS insulation layer is formed on the resultant structure including the metal interconnection wherein the void(4a) is generated between the metal interconnections. The PETEOS insulation layer is planarized. A TEOS layer of a single layer is deposited to form the PETEOS insulation layer by a plasma enhanced chemical vapor deposition(PECVD) method.
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