SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: A semiconductor memory device is provided to exactly generate a precharge enable signal and a write enable signal even though a size of a device changes. CONSTITUTION: An inverter(I3) and an inverter(I4) delay a precharge enable signal(S1) and generate a signal(S21). A NAND gate(NA2) performs a NAND operation of a signal(S3) and a column selecting signal(y1). A NOR gate(NOR) performs a NOR operation of an output signal of the inverter(I3) and an output signal of the NAND gate(NA2) to generate a signal(S41). The signal(S21) is generated in response to the precharge enable signal(S1). The signal(S41) is generated by performing a NAND operation of the write enable signal(S3) and the column selecting signal(y1) in response to the precharge enable signal(S1). A control signal generating circuit generates the precharge enable signal(S1) and a write enable signal(S3) in response to a clock signal and a write enable signal.