| 摘要 |
PURPOSE: A preset output buffer is provided to judge a status of a current output signal by directly connecting a bias level of an output signal to an internal circuit. CONSTITUTION: A first NOR gate(11) performs a NOR operation of an output enable bar signal and an address transition signal inverted by a first inverter(I11). A first NAND gate(13) performs a NAND operation of an output signal of the first NOR gate(11) and a signal delayed by second and third inverters(I12,I13). A second NOR gate(12) performs a NOR operation of an output signal of the second inverter(I12) and an output signal passed through a first resistor(R11). A third NOR gate(14) performs a NOR operation of an output signal of the second inverter(I12) and an output signal of the second NOR gate(12). A first PMOS transistor(P11) is coupled between a power supply(Vcc) and an output terminal(IOPAD) and operates according to an output signal of the first NAND gate(13). A first NMOS transistor(N11) is coupled between the output terminal(IOPAD) and a ground terminal(Vss) and operates according to an output signal of the third NOR gate(14).
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