发明名称 METHOD FOR MANUFACTURING CHIP-TYPE SOLID-STATE ELECTROLYTIC CAPACITOR
摘要 PROBLEM TO BE SOLVED: To form thin and uniform electrical insulating layers in a lead frame having unevenness. SOLUTION: In a capacitor element 2, a dielectric oxide coat, an electrolytic layer and a cathode layer are formed in the order on the surface of an anode member which has an anode leading-out wire 4 and is composed of valve action metal, and an outer periphery is made the cathode layer. In a lead frame 11, external terminals 5, 6 which are to be connected with the anode leading-out wires 4 and the cathode layers of the capacitor elements 2 to be mounted are installed, and the anode terminals 5 of the external terminals have protruding parts 20 which correspond to the heights from lower surfaces of the capacitor elements 2 to lower ends of the anode leading-out wires 4. In a method for manufacturing a chip-type solid-state electrolytic capacitor 1, the capacitor elements 2 are mounted on the lead frame 11, in such a manner that the external terminals 5, 6 are positioned below the mounted capacitor elements 2, the mounted capacitor elements 2 are covered with sheath resin, prescribed regions containing the capacitor elements 2 are cut out; and a prescribed shape is formed. A liquefied material, containing electrical insulating resin, is spread between the lower surface of the capacitor elements 2 and the anode terminals 5, by using an ink, jet head 30 having a plurality of continuously connected microjet nozzles, and electrical insulating resin layers 9 are formed.
申请公布号 JP2002175942(A) 申请公布日期 2002.06.21
申请号 JP20010291348 申请日期 2001.09.25
申请人 NIPPON CHEMICON CORP 发明人 FUNAYAMA YOSHIHIKO
分类号 H01G13/00;H01G9/00;H01G9/012;(IPC1-7):H01G9/012 主分类号 H01G13/00
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