发明名称 PHASE MATCHING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a phase matching circuit capable of absorbing phase fluctuation of a clock with a simple constitution without deteriorating data. SOLUTION: This circuit has a constitution for receiving a transmission clock outputted from a transmission circuit and transmission data synchronized with the transmission clock, and absorbing the phase shift between circuits operated with the same clock based on the transmission clock. Also, the circuit has a constitution equipped with a phase comparison circuit 106 for comparing the phases of the transmission clock and an internal clock after delay adjustment, a variable delay circuit 107 for always adjusting the delay quantity of the internal clock so that the phase difference between the transmission clock and the internal clock after delay adjustment is removed based on the phase comparison result, D-FF 104 for latching the transmission data at a timing synchronized with the internal clock after delay adjustment, and D-FF 105 for latching data of a first D-type flip-flop output at a timing synchronized with the internal clock.</p>
申请公布号 JP2002175271(A) 申请公布日期 2002.06.21
申请号 JP20000374034 申请日期 2000.12.08
申请人 MITSUBISHI ELECTRIC CORP 发明人 TAKIZAWA KOICHI;KUBO KAZUO;ICHIBAGASE HIROSHI
分类号 G06F13/42;G06F1/12;H03K5/00;H03K5/13;(IPC1-7):G06F13/42 主分类号 G06F13/42
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