发明名称 DIVIDING METHOD, DIVIDING CIRCUIT AND MULTIPLYING AND DIVIDING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a dividing method, a dividing circuit and a multiplying and dividing circuit capable of executing a division of a large figure at a high speed. SOLUTION: In the dividing circuit, a subtraction processing part 22 for executing a subtraction of a divisor from a dividend repeatedly is constituted of a plurality of subtraction blocks DBi for dividing data of an object of the subtraction into a plurality of data and performing a parallel processing for the data, and a carry to be transmission information to a higher rank block which is generated in each block DBi at the time of the subtraction is processed at the next time subtraction. Namely, because each data of a small bit width are independently processed in each block DBi, transmission time for the carry generated within each block, that is the time required for a subtraction of one time is shortened. A processing for the generated transmission information is performed together at the next time calculation without performing a new and independent calculation and thereby the repeating times of calculations is not increased.
申请公布号 JP2002175178(A) 申请公布日期 2002.06.21
申请号 JP20000371567 申请日期 2000.12.06
申请人 DENSO CORP 发明人 NAGURA MICHINAGA
分类号 G06F7/52;G06F7/506;G09C1/00 主分类号 G06F7/52
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