VERY LARGE SCALE INTEGRATED CIRCUIT AND METHOD FOR REDUCING NUMBER OF CLOCK CYCLES

摘要

PURPOSE: A very large scale integrated circuit and a method for reducing the number of clock cycles are provided to allow the circuit to operate at the falling edge as well as the rising edge of a clock. CONSTITUTION: A very large scale integrated circuit for reducing the number of clock cycles includes a plurality of processors(810,820,830,840) and a connector. The processors are alternately connected to be operated at the rising edge and falling edge of one clock. The connector alternately connects the plurality of processors. Each of the processors includes the first storage for storing input data, a calculation unit for calculating the absolute difference of input data items, and the second storage for storing the calculated absolute difference.