NON-SYNCHRONOUS FIFO CIRCUIT

摘要

PROBLEM TO BE SOLVED: To constitute a receiving FIFO(First In First Out) incorporated in start-stop synchronizing serial communication equipment holding interchangeability with a PC 16550D being an industry standard, using a general use memory- macro. SOLUTION: A well known non-synchronism FIFO circuit is provided with an error-write-counter 61 adding 1 when a word to which any of error flags is set is written, an error-read-counter 62 adding 1 when a word to which any of error flag is set is read out, and an error comparing circuit 63 comparing both values. Since an output of this error comparing circuit is made equivalent to LSR7 bits of the PC 16550D, interchangeability with the 16550D can be kept even if a memory 23 is constituted using a general purpose memory-macro.