发明名称 |
DATA PROCESSOR AND DATA PROCESSING METHOD |
摘要 |
PROBLEM TO BE SOLVED: To provide a data processor which is capable of enhancing data processing ability while reducing electric power consumption as far as possible. SOLUTION: In the data processor 1, a head 3 for a pickup reads data out of a memory medium 2. This data is transferred by a plurality of bit in a parallel state in synchronization with a clock signal to a controller section 5. The controller section 5 detects specific marks for synchronous detection included in the data in order to synchronize a series of the data received from a read channel section 4 and demodulates the data exclusive of the specific marks for synchronous detection. A mark detecting section 11 in the controller section 5 detects the specific marks for synchronous detection from the data in the parallel state received by a shift register 10. |
申请公布号 |
JP2002175672(A) |
申请公布日期 |
2002.06.21 |
申请号 |
JP20000370275 |
申请日期 |
2000.12.05 |
申请人 |
FUJITSU LTD;FUJITSU VLSI LTD |
发明人 |
YAMAWAKI MASASHI |
分类号 |
G11B20/14;G06F11/00;G11B20/10;G11B20/12;H03L7/00 |
主分类号 |
G11B20/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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