发明名称 Low resistance complementary metal oxide (CMOS) transistor and method
摘要 A method for forming a CMOS transistor with self-aligned cladding is provided that comprises forming a disposable gate structure (20) outwardly from a substrate (10) in a gate region (62) where the disposable gate structure (20) comprises a replaceable material (18). The method next provides for forming a source (40) and a drain (42) in the substrate (10) on opposite sides of the gate region (62). The method next provides for cladding the source region (40) and the drain region (42) using a self-aligned process. The method next provides for selectively removing the disposable gate structure (20), and forming a gate structure (70) in the gate region (62) vacated by the disposable gate structure (20). The method next provides for cladding a gate structure (70) using a self-aligned process.
申请公布号 US2002076885(A1) 申请公布日期 2002.06.20
申请号 US20000737310 申请日期 2000.12.14
申请人 CHEN IH-CHIN 发明人 CHEN IH-CHIN
分类号 H01L21/28;H01L21/336;H01L21/8238;(IPC1-7):H01L21/336;H01L21/20;H01L21/823;H01L21/338 主分类号 H01L21/28
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