| 摘要 |
The invention relates to a memory comprising a matrix (M L,K) of memory units and a memory controller ( 104) that is connected to the common conductor (CLk) and to the column conductor (BLk) and designed to selectively read each memory cell (PMCI,k) by closing the switch (TI,k) associated with the memory cell (PMCI,k) being written, opening the switches (TI,k) associated with the other memory cells (PMCI,k) of the column (k) of the memory cell (PMCI,k) being written, and measuring a current circulating in the common conductor (CLk) and the column conductor (BLk) and passing through the memory cell (PMCI,k) being written. The memory comprises a resistance adjustment system ( 106) designed to apply an adjustment signal that has a first value if the switch (TI,k) is in the closed reading position, and a second value, different from the first value, if the switch (TI*,k*) is in the open reading position. |
