发明名称 SUBTHRESHOLD CMOS INTEGRATOR
摘要 An integrator circuit having a relatively large RC time constant includes a resistive element implemented with a field effect transistor operated in a sub-threshold mode. The size of the field effect transistor is selected, in addition to the sub-threshold gate voltage, to achieve a desired resistance value in a small area and without using bipolar devices. A differential integrator circuit includes two field effect transistors operated in a sub-threshold mode, with a capacitor connected between the output terminals of the two field effect transistors. A bulk drive circuit can be optionally used to reduce high frequency in the bulk.
申请公布号 US2002075056(A1) 申请公布日期 2002.06.20
申请号 US20000740296 申请日期 2000.12.18
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 SAUER DON
分类号 G06G7/186;(IPC1-7):G06G7/18 主分类号 G06G7/186
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